Carlos Georges | GPU Physical Design Engineer

About

I build GPU silicon at Intel and think about how to make the whole process smarter. My day-to-day spans power delivery, UPF methodology, and signoff — but the part I keep coming back to is automation: building AI agent frameworks that can take a design spec and turn it into an optimized physical block without a human in the loop.

I got here through range. I started by tutoring math, built microprocessors and rescue robots in undergrad, wrote firmware for gaming machines, led flight software for a CubeSat, and shipped a research platform for a medical journal — none of which I was formally trained for. That pattern is the point: I learn whatever the problem requires, then build the system that solves it.

Columbia MSEE, UNLV Computer Engineering (3.93). Three languages. The through-line is the same whether I'm closing power on a GPU block or wiring up an AI pipeline — I want to understand the full stack, then make it better.

Languages English (Native) · Arabic (Native) · Spanish (Fluent)

Technical Skills

Core

Python TCL Linux Fusion Compiler Cadence Virtuoso

HDL & Verification

Verilog SystemVerilog Synopsys VCS

Programming

Perl C / C++ C#

Domains

Physical Design UPF / Power Intent Power Delivery RTL Synthesis Timing Closure Agentic AI

Highlights

Published Research

A research team needed a data platform and I was the only engineer in the room. Built the full stack — GUI to cloud pipeline — co-authored the paper in the Journal of Medical Education and Curricular Development, and presented at the AAMC Western Group conference. Not my field. Didn't matter.

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Featured on NBC News

Senior capstone project: an autonomous rescue robot using computer vision and AI to find people and clear debris in disaster scenarios. The kind of problem where hardware, software, and real-world constraints all collide — which is exactly where I work best.

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GPU Program Analytics

Hundreds of GPU partitions across datacenter and client programs, five project leads, and no unified way to track quality. I built the QoR dashboard system that gave the team week-over-week visibility and made it the backbone of our design decisions.

Agentic AI for Chip Design

The chip design pipeline is still heavily manual. I'm building the AI agent framework to change that — a system that takes a design spec and drives it through RTL-to-GDS with minimal human intervention. Early days, but this is where silicon is headed.

Get in Touch

Always interested in hard problems at the intersection of silicon and AI. Let's talk.

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